SOC Verification Engineer @ UST

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SOC Verification Engineer

UST
4 - 12 years
Bengaluru
3 days ago
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Job Description

Roles and Responsibilities :

Design and develop testbenches using SystemVerilog, UVM, and PCIe protocol for SOC verification.
Collaborate with cross-functional teams to identify requirements and create test plans, cases, and scenarios.
Develop GPIO drivers and monitors to interface with external devices during testing.
Analyze results, debug issues, and provide detailed reports on test execution.

Job Requirements :

4-12 years of experience in SOC verification engineering.
Strong understanding of C programming language for scripting tasks.
Proficiency in System Verilog, UVM, PCIe protocols for design verification.

Job Classification

Industry: IT Services & Consulting
Functional Area / Department: Engineering - Software & QA
Role Category: Software Development
Role: Software Development - Other
Employement Type: Full time

Contact Details:

Company: UST
Location(s): Bengaluru

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Keyskills: SOC Verification UVM System Verilog C Programming Language PCIE Gpio

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Expected Salary (*)

Desired Industry (*):

Functional area / Department (*):

Enter Skills (key skills, subjects, technologies & roles to use in search)

Write briefly about yourself, your experience and education (*)

Attach ResumeMax 2.38 MB (RTF, PDF, DOC, DOCX formats only parsed)

Please, check the file size and type.

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Create password

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SOC Verification Engineer @ UST

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