Asic Rtl Engineer (rtl - Design Coding Integration Ip Soc)
Greetings from for the Day
We have challenging roles at WIPRO, Please find the below active requirement.
Please share your updated resume if your interested to apply for the current roles.
ASIC RTL Engineer (RTL Design, RTL Coding & Integration, IP, targeted for SOC, Static checks, Protocols - PCIe, DDR, Ethernet,I2C, UART, SPI)
Experience : 6 Years 22 Years
Work Location : Bangalore / Hyderabad / Kochi / Pune
Work Mode : Hybrid (3 days Work From Office)
Employment Type : Full Time with Wipro
Expertise in SoC subsystem/IP design
Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog
In depth knowledge on RTL quality checks (Lint, CDC)
Knowledge of synthesis and low power is a plus
Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB)
Good understanding of timing concepts
Knowledge of one or more of the interface protocols
a. PCIe
b. DDR
c. Ethernet
d. I2C, UART, SPI
Expertise in setting up and using tools like
a. Spyglass Lint/CDC
b. Synopsys DC
c. Verdi/Xcellium
Understanding of scripting languages like Make flow, Perl ,shell, python etc
Understanding of processor architecture and/or ARM debug architecture is a plus
Able to help and debug issues for multiple subsystems
Able to create/review design documents for multiple subsystems
Able to support physical design, verification, DFT and SW teams on design queries and reviews
Kindly share your Updated Resume with Below Details to: Email - sw*************n@wi**o.com
Kindly refer or circulate this opportunity with your colleagues /friends who are seeking for challenging role.
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