PNR Lead
- ACL Digital
- 8 - 10 years
- Bengaluru
- 10 months ago
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Job Description
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About Us
Roles and Responsibility
Technical Skills:
Should be able tohandle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring,package support, multi voltage design
Deep understandingof the concepts related to synthesis, place & route, CTS, timingconvergence, IR/EM checks and signoff DRC/LVS closure
Responsibilities Responsible forindependent planning and execution of all aspects of physical design includingfloor planning, place and route, Clock Tree Synthesis, Clock Distribution,extraction, Timing closure, Power and Signal Integrity Analysis, PhysicalVerification, DFM
Must haveparticipated in all stages of the design (floor planning, placement, CTS,routing, physical verification, IREM)
Well versed with thetiming closure (STA), timing closure methodologies
Good Understandingof DRC, LVS,ERC and PERC rule files for lower tech node layout verification
Experience in lowertech node (
Good automationskills in PERL, TCL and EDA tool-specific scripting
Able to takecomplete ownership for Block/sub-system for complete execution cycle
Out of box thinkingto meet tighter PPA requirements
Able to takecomplete ownership for Block/sub-system for complete execution cycle
Out of box thinkingto meet tighter PPA requirements
Job Classification
Industry: IT Services & ConsultingFunctional Area / Department: Engineering - Hardware & NetworksRole Category: HardwareRole: Design Team LeadEmployement Type: Full timeContact Details:
Company: ACL DigitalLocation(s): Bengaluru+ View Contact
Keyskills: Automation Timing closure Product innovation Consulting Physical verification Perl Floor planning Signal integrity Physical design
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