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Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems
At the core of our mission lies a culture of innovation
We challenge boundaries to solve some of the world''s most critical problems
We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way
Responsibilities
Build RTL/BV wrappers/write behavior models for Analog and mixed signal designs
Create Test benches and perform simulations at block level and system level to validate RTL/BV model correctness with respect to Schematics
Collaborate with cross-functional teams to achieve project milestones.
Debug and troubleshoot the RTL/BV model issues by working with Analog circuit designers.
Perform LEC/LINT/ESP analysis
Skills
Must have
3-5y exp
Experience in RTL front-end design with some circuit design knowledge.
Understanding of Timing Concepts, Analog circuits at a holistic level
Strong analytical and problem-solving skills.
Excellent verbal and written communication skills.
Experience in RTL-based simulations using VCS, usage of Verdi, formal verification, LEC/LINT/ESP analysis
Knowledge of scripting languages & automation tools (Perl, TCL, Skill, Ocean, Python) is an added advantage
Nice to have
Effective communication and problem-solving skills.
Job Classification
Industry: LegalFunctional Area / Department: Engineering - Hardware & NetworksRole Category: HardwareRole: Design Verification EngineerEmployement Type: Full time