Lead DFT Engineer
- VMware
- 6 - 10 years
- Bengaluru
- 23 days ago
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Job Description
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The position requires an energetic, proactive, self- starting person, who is able to lead and coordinate full chip DFT task and work closely with other DFT engineers to explor e new methodologies. You must possess strong technical kn owledge in the area of design-for-test (DFT). Design for Test Engineer to perform any of the follo wing ASIC design tasks: - Develop best in class, highest quality DFT methodol ogies for all design teams in meeting all test requirements & silicon quality standards - Implement/design/validate all DFT RTL/IP, required by all designs. - Drive latest DFT tools to produces highest quality DFT RTL/IP. - Drive ATPG generation/validation. - Work with RTL design, test engineering teams to imp lement highest quality DFT implementation. - Verify chip design for all DFT requirements, this i ncludes DFT functional verification, DFT coverage verification a nd static timing analysis. - Static Timing/Noise/Coupling Analysis for test mod es at chip level. - Generating clear documentation & easy to use scrip ts to support DFT flows. - Evaluation of tools in the development of DFT flow s. - Responsible for day to day coordination of DFT des ign activity and resources, in meeting project schedules . - work with ATE test engineers to debug production te st patterns
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Job Classification
Industry: Software ProductFunctional Area / Department: Engineering - Hardware & NetworksRole Category: HardwareRole: ASIC / RTL / Logic Design EngineerEmployement Type: Full timeContact Details:
Company: VMwareLocation(s): Bengaluru+ View Contact
Keyskills: RTL design ASIC Quality standards DFT Chip design atpg Silicon Test engineering Testing
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