Senior Test Engineer - Engineer
- Happiest Minds
- 3 - 5 years
- Bengaluru
- 3 months ago
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Job Description
Verification of RTL designs for FPGA -Block/subsystem/chip/system level functional verification
-Implement verification environment in SV using UVM methodology according to the architecture specification
-Development and execution of test cases -Report test results and assist in RTL debug using simulation
-3 - 6 years of hands-on experience of verification in customer projects
-Bachelors/Masters in Electronics Engineering
-Strong communication skills mandatory
Job Classification
Industry: IT Services & ConsultingFunctional Area / Department: Engineering - Software & QARole Category: Quality Assurance and TestingRole: Post Silicon Test EngineerEmployement Type: Full timeContact Details:
Company: Happiest MindsLocation(s): Bengaluru
Keyskills: soc verification c++ usb test case execution test cases project vhdl test engineering rtl design axi linux rtl coding debugging ahb i2c perl system verilog protocols verification communication skills python asic verification c software testing uvm spi verilog uart pcie
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