STA Lead
- Team Computers
- 5 - 8 years
- Bengaluru
- 4 months ago
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Job Description
We are seeking an experienced Full-Chip STA Engineer to drive timing closure and sign-off across the entire SoC/ASIC design. The role requires expertise in multi-block integration, multi-mode/multi-corner analysis, and sign-off methodology for advanced technology nodes.
Key Responsibilities:
- Perform full-chip static timing analysis for all functional and test modes across multiple PVT corners.
- Own SDC constraint generation, validation, and refinement at top-level.
- Collaborate with block-level STA, physical design, synthesis, and clock teams to achieve timing closure.
- Debug and resolve full-chip setup/hold violations through ECOs, floorplan changes, and clock optimizations.
- Conduct MMMC (Multi-Mode, Multi-Corner) timing analysis, including OCV, AOCV, and POCV variations.
- Integrate timing reports from multiple blocks, perform hierarchical timing closure, and ensure sign-off compliance.
- Work with DFT teams to analyze scan shift and at-speed test timing.
- Automate report generation, violation tracking, and closure metrics using Tcl, Perl, or Python.
- Provide guidance on timing budgets for IP/block owners.
- Interface with foundries and EDA vendors to resolve tool and library issues.
Job Classification
Industry: Electronic Components / SemiconductorsFunctional Area / Department: Engineering - Hardware & NetworksRole Category: HardwareRole: Physical Design / Layout EngineerEmployement Type: Full timeContact Details:
Company: Team ComputersLocation(s): Bengaluru
Keyskills: OCV STA MMMc Synthesis EDA Timing Closure Chips Static Timing Analysis SCAN TCL AOCV
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Team Computers Pvt. Ltd. Team Computers Pvt. Ltd. Incorporated in 1987, Team has completed 31 successful years of building trust and has emerged as a leading IT solutions provider, supporting more than 1800 customers across the country. At Team, we look at ourselves as a bridge between the wo...
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