Analog IP: PLL, BG, LDO, OpAmps etc.
Power Management IP: Low Voltage and High Voltage LDO, BG, DC - DC Buck, DC - DC Boost, DC - DC Buck - Boost, and Charge Pumps etc.
Part B: Essential Responsibilities Include:
Analog IP: PLL, BG, LDO, OpAmps etc.
Power Management IP: Low Voltage and High Voltage LDO, BG, DC - DC Buck, DC - DC Boost, DC - DC Buck - Boost, and Charge Pumps etc.
The responsibility includes complete understanding of circuit topologies, best class architecture development, Design from Specifications, Sub - Block circuit design, layout or guidance to layout effort and review etc.
Part C: Please complete the following Objectives Questionnaire:
You will work directly with existing team working on circuit architecture development from spec, IP - Level/Block - Level Circuit Design, Simulations, Results Documentation for review, PDK assessment with IP, Layout Design and Layout verification. The assignment would involve getting exposure to leading edge foundry EDA tools, design flows, and yield / design interaction.
Required Qualifications:
MSEE or PhD from an accredited program on Electronics Engineering, Microelectronics with focus on the mentioned circuits.
BE/B.Tech + (4 - 5) years
MS/MTech (0 - 2) years
Minimum of 3 months experience with UNIX environment.
Excellent academic standing.
Attention to detail and Learning skills
Self - motivated; able to take ownership of assignments, develop work plans and proactively seek feedback to ensure objectives are aligned and met.
Strong written and oral communications skills.
Team player; able to succeed in a dynamic, fast paced environment.
Preferred Qualifications:
PhD/M.Tech Student from reputed academic Institutes in India (Ex: IITs or NITs or BITs))
Experience with any domain listed above in Part B.
Familiarity with Cadence based packaging and Cadence,PADS PCB design system tools.
Keyskills: Unix Semiconductor RF design Development Manager Pumps Power management Analog Circuit designing Packaging PCB designing
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