STA Engineer
- Capgemini
- 3 - 7 years
- Hyderabad
- 5 months ago
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Job Description
We are seeking a highly skilled and experienced Physical Design Engineer to join our team. The ideal candidate will have hands-on experience in chip-level and block-level physical design, timing closure, and signoff processes. This role requires proficiency in industry-standard tools and scripting, along with a strong understanding of design constraints and methodologies. Key Responsibilities: Perform chip-level floorplanning, partitioning, timing budget generation, and power planning.Execute top-level place and route (PnR), clock tree synthesis (CTS), block integration, and ECO generation.Handle block-level implementation from netlist to GDSII.Drive timing closure for high-frequency blocks and manage blocks with high instance counts (1M+).Ensure signoff closure for timing (including SI and OCV), power, IR drop, and physical verification.Apply signal integrity (SI) prevention and fixing methodologies.Conduct layout edits and physical design optimizations.Automate design tasks and manage UNIX-based environments. PrimarySkills:
Skills:
Job Classification
Industry: IT Services & ConsultingFunctional Area / Department: Engineering - Hardware & NetworksRole Category: HardwareRole: Hardware Platform EngineerEmployement Type: Full timeContact Details:
Company: CapgeminiLocation(s): Hyderabad
Keyskills: physical design unix system perl closure editing c++ socket programming sql plsql unix shell scripting drc linux shell scripting tcl synthesis sta cts primetime lvs 185114 signal integrity floor planning timing closure pnr synopsys vlsi unix
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Capgemini is a global business and technology transformation partner, helping organizations to accelerate their dual transition to a digital and sustainable world, while creating tangible impact for enterprises and society. It is a responsible and diverse group of 340,000 team members in more than 5...
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