-Role & responsibilities
Sr. Memory Layout Engineer
JOB DESCRIPTION
-Hands on experience on different Memory Leafcells like IO/xdec/predec layout design, from -scratch including memory top level integration.
Sound knowledge & hands on experience in Finfet technology, preferably N4/N3/N2.
-Good knowledge on different types of memory architectures.
-Good knowledge in optimized layout design for better performance.
-Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions.
-Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow.

Keyskills: 3nm and FinFET technologies.
Tech Mahindra Limited is an Indian multinational provider of information technology (IT), networking technology solutions and Business Process Outsourcing (BPO) to the telecommunications industry. Tech Mahindra is a US$4.2 billion company with over 117,000 employees across 90 countries. It provide...