Verification Engineer
- Luxoft
- 4 - 6 years
- Hyderabad
- 5 months ago
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Job Description
Responsibilities
- Develop System Verilog/UVM-based testbenches for block-level and system-level verification.
- Write and execute UVM test cases to verify functional correctness of RTL designs.
- Perform detailed functional coverage and code coverage analysis, and drive coverage closure.
- Debug simulation failures, root-cause issues, and work closely with design and verification teams for resolution.
- Collaborate with cross-functional teams to ensure successful verification closure within project timelines.
- Develop and maintain scripts using Python or other scripting languages for automation, regression management, and data analysis (optional but preferred).
- Apply working knowledge of standard bus protocols such as AXI, APB, UART, and IJTAG for testbench development and debugging.
- Document verification plans, test specifications, test reports, and maintain traceability.
Skills
Must have
- 4-6y exp
- SV / UVM Test bench development and test cases coding
- Code and Functional coverage analysis and closure
- Work with team for verification closure
- Bus protocols AXI / APB / UART/ IJTAG protocol working knowledge is an advantage.
- Nice to have
- Experience with python or any other scripting language is a plus
Notice Period: Till 30 Days
Job Classification
Industry: LegalFunctional Area / Department: Engineering - Hardware & NetworksRole Category: HardwareRole: Functional Verification EngineerEmployement Type: Full timeContact Details:
Company: LuxoftLocation(s): Hyderabad+ View Contact
Keyskills: python RTL designs AXI APB Verification Engineering UART UVM Test IJTAG
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