1. Solid experience in place & route flow (placement guidelines, clock-tree synthesis, routing, timing optimizations).
2. Experience on hierarchical designs and/or Low Power implementation is an advantage.
3. Experience on Synthesis, interfacing with RTL and implementation
4. Experience on Floorplan design, including placement of hard macros, congestion reduction techniques.
5. Experience on Static Timing Analysis related activities , parasitic extractions, sign-off requirements).
6. Knowledge of Physical Verification (DRC/LVS/DFM, chip finishing) is an added advantage

Keyskills: Design For Manufacturing STA Cts Chips ICC LVS DFM Primetime Innovus Interfaces Low Power Design Physical Verification Synthesis Floor Planning DRC Placement PNR Timing Closure Floorplan Physical Design TCL
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