ASIC Design Verification Engineer
- Cisco
- 7 - 8 years
- Bengaluru
- 9 months ago
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Job Description
- Architect block, cluster and top-level DV environment infrastructure.
- Develop DV infrastructure from scratch for block, cluster and top-level environments.
- Maintain and enhance existing DV environments.
- Develop test plans and tests for qualifying design at block, cluster and higher-level environments with mix of constraint random and directed stimulus.
- Ensure complete verification coverage through implementation and review of code and functional coverage.
- Ensure RTL quality with qualifying the design with Gate Level Simulations on netlist.
- Collaborate closely with designers, architects, and software teams to address and debug issues during post-silicon bring-up, ensuring seamless integration and optimal performance.
- Support testing of design in emulation.
- Oversee and manage the ASIC bring-up process.
Minimum Qualifications
- Bachelor s Degree in EE, CE, or other related field.
- 7+ years of related ASIC design verification experience.
- Proficient in ASIC verification using UVM/System Verilog.
- Proficient in verifying complex blocks, clusters and top level for ASIC.
- Experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes.
- Scripting experience with Perl and/or Python.
Preferred Qualifications
- Master s Degree in EE or CE with 5+ years of related work experience.
- Experience with Forwarding logic/Parsers/P4.
- Experience with Veloce/Palladium/Zebu/HAPS.
- Formal verification (iev/vc formal) knowledge.
- Domain experience on one or more protocols (PCIe, Ethernet, RDMA, TCP).
Job Classification
Industry: IT Services & ConsultingFunctional Area / Department: Engineering - Hardware & NetworksRole Category: HardwareRole: Design Verification EngineerEmployement Type: Full timeContact Details:
Company: CiscoLocation(s): Bengaluru+ View Contact
Keyskills: TCP Wireless ASIC Networking Ethernet Perl System verilog PCIE cisco Python
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