Mixed Signal Asic Design Lead - System Verilog @ Synopsys

Job Description

Lead and coordinate a team of 5 engineers in mixed-signal, RF, analog and digital domain Design and guide projects on advanced mixed-signal circuits data converters, sub-sampling phase locked loops, serdes and RF circuits in CMOS and BiCMOS and low-power & low-voltage applications. Skilled in Cadence custom IC EDA tools. Knowledge of Keysight Pathway desired. Achieve successful realization of the layout in close collaboration with layout team. Work with application developers to co-develop hardware and software systems. Collaborate with teams in India and abroad during project implementation phase. Requirements PhD/Master degrees from top universities Must have a Proven track record of taking multiple mixed-signal ICs through the entire development cycle, from concept to production. + 10 years" experience industrial experience in analog and mixed-signal. design. Successful realization of more than 5 ASIC designs In depth knowledge of Cadence custom IC EDA tools Proficiency in system and behavioural modeling using MATLAB, System Verilog, Verilog-A/AMS. Experience with HDL languages Verilog and/or VHDL is desired. Scripting skills like Python, Perl and C is a plus. Experience with design, implementation, and development environments for reconfigurable systems (such as FPGAs) is a plus. Experience with the silicon manufacturers and working with various CMOS process technologies is a plus. (ref:hirist.tech

Employement Category:

Employement Type: Full time
Industry: Engineering / Construction
Role Category: Engineering / Construction
Functional Area: Not Applicable
Role/Responsibilies: Mixed Signal Asic Design Lead - System Verilog

+ View Contact

Keyskills:   RF Analog Digital CMOS BiCMOS Layout design MATLAB System Verilog Verilog VHDL Python Perl C Mixedsignal ASIC Design Cadence custom IC EDA tools Keysight Pathway Hardware software systems codevelopment System behavioural modeling VerilogAAMS HDL languages FPGAs CMOS process technologies