Design Verification, C , C++
Work location: Noida o Proficient in C, C++ programming and scripting languages
o Familiar with Functional verification using Verilog/System Verilog/UVM
o Good understanding of Memory/Networking/Bus based protocols
o VIP development experience will be an added advantage
o Should possess strong analytical and communication skills Qualification - BE/B.Tech/M.E./M.Tech or equivalen
Keyskills: Design verification C++ C Networking Lead Software Analytical Manager Technology System verilog UVM Scripting
Pannal (a brand of Cadence Partners LLP) is a shared-services consultancy firm helping startups and companies across various stages. We offer diverse resources under one roof including professional services, business support, finance & accounting, recruitment & HR services, legal...