Please share me the profiles for the below SSOC DFT SCAN/ATPG engineer requirement with 5+ years of experience. Have two Open Positions for Bangalore.
Scan insertion
SCAN DRC/Coverage debug
ATPG Pattern generation
Gate level simulations ( Zero delay/Timing Delay simulations)
Worked on JTAG/P1500 protocols
Perl/Tcl scripting
Timing/Formal verification/PD flow knowledge is plus
Job Classification
Industry: IT Services & ConsultingFunctional Area / Department: Engineering - Hardware & NetworksRole Category: HardwareRole: Head - Hardware EngineeringEmployement Type: Full time