Full Stack - Senior Tech Lead @ ACL Digital

Responsible for Full Chip STA/timing closure.

SoC Top STA - handling Runs / Providing Feedback on Setup/hold/TDRC to the PD team.

5+ years of experience in STA or timing related tasks.

Should have good exposure to high frequency multi voltage design convergence.

Good understanding of clock networks.

Constraint development and validation

Work with PD owner to provide timing feedback at placement/CTS/Routing stages

we'll versed with Synopsys PrimeTime or Cadence Tempus or equivalent timing closure tool

Generate timing eco for final timing closure using DMSA/Tweaker

we'll versed with Tcl/Perl scripting