DFT Engineer
- ACL Digital
- 5 - 10 years
- Bengaluru
- 9 months ago
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Job Description
Roles and Responsibility
5 years to 15 yrsdesign experience. Experience withowning chip level DFT and Post Silicon debug / analysis.
Desired Skills:
Understanding of DFTarchitectures like JTAG, Scan Compression Techniques (XOR, Adaptive, OP-MISRetc.), scan chain insertion and verification.
Must have experiencegenerating scan patterns and coverage statistics for various fault models likestuck at(Nominal and VBOX), IDDQ, Transition faults, JTAG BSDL, patterngeneration for Memories(E-fuse etc.). Experience debugging tester failures ofscan patterns, diagnosis and pattern re-generation. Understandinggeneration of functional patterns for ATE
Knowledge of atleast any one of an industry standard DFT tools (Cadence Modus, SynopsysTetramax, Mentor Tessent Tools, etc)
Design experience inMBIST / LBIST is an added advantage.
Good understandingof constraints development for Physical Design Implementation / Static TimingAnalysis.
Responsibilities:
- Must have experience generating scan patterns andcoverage statistics for various fault models like stuck at(Nominal and VBOX),IDDQ, Transition faults, JTAG BSDL, pattern generation for Memories(E- fuseetc.). Experience debugging tester failures of scan patterns, diagnosis andpattern re-generation.
- Understanding generation of functional patterns forATE
- Knowledge of at least any one of an industrystandard DFT tools (Cadence Modus, Synopsys Tetramax, Mentor Tessent Tools,etc)
- Design experience in MBIST / LBIST is an addedadvantage.
- Good understanding of constraints development forPhysical Design Implementation / Static Timing Analysis.
Desired Skills:
- Preferred Skills/ Experience
- Experience with TCL / Perl is preferred.
- Understanding of IC design with Analog circuits andit s design cycles is an added advantage.
- Effective communication skills to interact with allstakeholders.
- Team and People Skills: The candidate should havegood people skills to work closely with the systems, analog, layout and testteam
- Must be highly focused and remain committed toobtaining closure on project goals
Job Classification
Industry: IT Services & ConsultingFunctional Area / Department: Engineering - Software & QARole Category: Quality Assurance and TestingRole: Post Silicon Test EngineerEmployement Type: Full timeContact Details:
Company: ACL DigitalLocation(s): Bengaluru+ View Contact
Keyskills: JTAG DFT static timing analysis Product innovation Consulting IC design Perl Silicon Analog layout Physical design
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