Asic Frontend Implementation, Cdc/rdc @ Meta

Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC.
Perform Flat and Hierarchical Reset Domain crossing Checks. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC.
Perform RTL Lint and work with the Designers to create waivers.
Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults.
Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power.
Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC,).
Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback.

Bachelors degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
8+ years of experience in static verification tools
Experience with Lint, Clock Domain & Reset Domain crossing.
Knowledge of SOC Integration (Clocking, Reset, PLL, etc)
Knowledge of front-end ASIC flows
Experience with RTL design using SystemVerilog or other HDL.
Bachelors degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
5+ years of experience in static verification tools
Experience with communicating across functional internal teams and vendors.
Experience with Lint, Clock Domain & Reset Domain crossing
Experience with SOC CDC signoff
Knowledge of SOC Integration (Clocking, Reset, PLL, etc)
Knowledge of front-end ASIC flows
Experience with RTL design using SystemVerilog or other HDL.
Experience with communicating across functional internal teams and vendors.

Experience with SOC Design Integration and Front-End Implementation
Knowledge of Timing/physical libraries, SRAM Memories.
Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools.
Experience with Netlist-CDC Analysis and improving MTBF
Experience with developing structural rule based checks for RTL & Netlist
Scripting and programming experience using Perl/Python, TCL, and Make
Experience with SOC Design Integration and Front-End Implementation.
Knowledge of Timing/physical libraries, SRAM Memories.
Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools.
Experience with Netlist-CDC Analysis and improving MTBF
Experience with developing structural rule based checks for RTL & Netlist
Scripting and programming experience using Perl/Python, TCL, and Make.

About Meta

Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today beyond the constraints of screens, the limits of distance, and even the rules of physics.

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