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Job Description:+ Full-time
+ IC role
+ Verify a block or a functional feature and lead it to closure.
+ Write and architect scalable and re-usable testbenches from scratch, using the framework of the verification methodology
+ Create test cases, functional coverage models and bring the verification to closure
+ Think differently and out-of-the-box to stress the DUT and verify it in an efficient way.
+ Be involved in documenting verification strategy including test plans, verification micro-architecture, coverage objects etc.
+ Participate and own verification strategic decisions that will help in long run.
Mandatory Requirements:
+ BS/BE degree in Engineering.
+ More than 10 years of experience writing and debugging test benches
+ Must have deep understand of full ASIC cycle, right from conceptualization to TapeOut.
+ Must have proficiency in constrained random verification methodologies like UVM/VMM/OVM
+ Must be proficient with System Verilog
+ Should have exceptionally good command over fundamental OOP principles.
+ Should be open to learning verification methodologies and strategies, that may be cutting edge but different from the industry standard.
+ Motivated and self-driven.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Keyskills: ASIC ASIC Verification Debugging VMM Conceptualization System verilog Test cases UVM Testing
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