VLSI Technical Design and Verification Engineer @ VMware

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PCIe Architect/System Design Engineer:

Job Summary:

We are seeking a highly experienced PCIe Architecture and Systems Engineer to join our ASIC Product Division team. The ideal candidate will have a deep understanding of System architectures, system design, and various communication protocols such as PCIe, CXL and AMBA/AXI. This role involves designing, implementing, and optimizing PCIe solutions for complex SoC (System on Chip) designs, collaborating with cross-functional teams, and driving research and development initiatives to stay at the cutting-edge technologies.

Key Responsibilities:

• Architecture Design: Develop and optimize PCIe architectures for high-performance SoC designs, including switches, interconnects, and communication protocols.
• Protocol Expertise: Design and implement PCIe solutions that support various communication protocols such as PCIe, CXL and AMBA/AXI.
• System understanding: Understanding of PCIe solutions for overall SoC design, ensuring seamless communication between various IP blocks and subsystems.
• Performance Analysis: Conduct detailed performance analysis and benchmarking of PCie designs to identify bottlenecks and areas for improvement.
• Collaboration: Work closely with hardware, software, and verification engineers to ensure that PCie designs meet system requirements and performance goals.
• Troubleshooting: Identify and resolve complex issues in PCIe design and simulation.
• Research and Development: Stay updated with the latest advancements in PCIe Specifications and contribute to the development of new standards/methodologies and tools. Actively participate in research projects to explore new PCIe Programs and protocols.

Primary Skills

• Proficient in PCIe design and optimization techniques.
• Strong understanding of digital design principles and SoC architecture.
• Experience with hardware description languages (HDLs) such as Verilog, System-Verilog
• Knowledge of RTL simulation tools and Verification environments (e.g., Cadence, Synopsys, UVM).
• Expertise in various communication protocols such as PCIe, CXL, and Amba/AXI.

Soft Skills

• Excellent problem-solving and analytical skills.
• Strong communication and collaboration abilities.
• Ability to work independently and in a team environment.
• Attention to detail and a commitment to quality.
• Enthusiasm for research and development.

Preferred Skills:

• Experience with PCIe Gen-4/5/6 protocol skills
• Knowledge of ASIC design flows.
• Familiarity with scripting languages (e.g., Python, Perl).
• Experience with version control systems (e.g., Design-sync, Git).
• Background in PCie design, PCie Architecture and Serdes concepts, low-power design and optimization.
• Synthesis Tools like (DC/DC-NXT) or Fusion compiler
• Synthesis Constraints and Timing Concepts (STA)
• Spyglass (lint, DFT, PM, CLK/RST, CDC/RDC)
• Formal Verification check like Formality or Conformal LEC)
• Publication history in relevant technical journals/IEEE/ conferences is a plus

Qualifications:

Education: Bachelor s or Master s degree in Electronics and communication Engineering or Computer Engineering, or a related field.

Experience: 15 to 20 years of experience in PCIe architecture and systems design.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

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