ASIC Engineer Staff - Bengaluru/Bangalore @ Juniper Networks

Responsibilities :

1. Lead and execute the full-chip timing sign-off process for complex ASIC designs, ensuring the designs meet the required performance goals.
2. Collaborate with design and physical design teams to develop and refine timing methodologies and strategies.
3. Perform static timing analysis (STA) using PrimetimeSI/Tempus and develop timing constraints for full-chip designs, including block-level and top-level hierarchies.
4. Work closely with physical design teams to optimize floor-planning, placement, and routing for timing closure.
5. Drive timing closure activities, including timing constraint development, validation and ECO cycle
6. Perform comprehensive timing sign-off checks, including setup/hold, Noise, clock domain crossing.
7. Stay updated with industry trends and emerging technologies related to timing sign-off methodologies, tools, and techniques.

Qualifications:

1. Bachelors or Masters degree in Electrical Engineering or a related field. Advanced certifications are a plus.
2. Extensive experience (typically 11+ years) in ASIC Physical Design and timing closure, with a focus on full-chip sign-off.
3. In-depth knowledge of static timing analysis (STA) concepts, including clock tree synthesis, delay calculation, and optimization techniques and Crosstalk analysis and fixes.
4. Must have in-depth knowledge of Timing modes , corners , their optimization and prioritization and Sign-off requirements .
5. Strong expertise in timing analysis and closure tools, such as PrimeTime SI, or similar industry-standard tools.
6. Good knowledge of ECO generation to fix various timing violations with scripting or with automated ECO generation tools.
7. Must have worked and be proficient with Industry standard Physical design tools like Innovus, icc2/fusion compiler .
8. Proficient in scripting languages like Tcl, Perl, or Python to automate tasks and develop custom flows.
9. Must have involved in Timing sign-off for at least 2-3 ASIC/SOCs.
10. Solid understanding of ASIC design principles, RTL coding, and synthesis process.
11. Familiarity with industry-standard EDA tools and methodologies for physical design .
12. Excellent problem-solving skills and the ability to debug and resolve complex timing-related issues.
13. Strong communication and interpersonal skills, with the ability to collaborate effectively with cross-functional teams.
14. Experience in low-power design and power-aware timing closure is desirable but not mandatory.