Staff Engineer - AMS Verification - Pune
- Cyient
- 7 - 10 years
- Pune
- 11 months ago
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Job Description
Job Description
Experience:7+ years
AMS Verification Engineer - modeling using System Verilog, Wreal modeling, mixed-signal and mixed-mode verification, full-chip circuit simulation experience using SPICE, SPECTRE, HSIM, or equivalent tools as well as RTL verification
- BE/B.Tech in ECE /M.Tech in VLSI with 6 to 9 years experience in Analog Mixed Signal Verification
- Very Good experience in Verilog AMS, Verilog-A, WREAL, modeling of Analog blocks
- Very Good experience in Analog Mixed Signal verification simulation tools
- Good experience in System Verilog, UVM methodologies
- Able to train the team members and guide them to the solutions for problems
- Good experience in creating the AMS Verification environment and able to create AMS Verification environment from scratch.
- Good experience in Gate level netlist simulation
- Experience in Python, Perl, Shell scripting is added advantage.
- Good communication and documentation skills
Job Classification
Industry: Electronic Components / SemiconductorsFunctional Area:
Role Category: Engineering & Manufacturing
Role: Engineering & Manufacturing
Employement Type: Full time
Education
Under Graduation: Any GraduatePost Graduation: Any Postgraduate
Doctorate: Any Doctorate
Contact Details:
Company: Cyient LimitedLocation(s): Pune
Keyskills: Analog Mixed Signal Verification Verilog AMS UVM System Verilog mixed signal verification
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