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Senior DFT Engineer @ Cyient

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 Senior DFT Engineer

Job Description

Job Location: Hyderabad, Bangalore, Pune. (Upcoming Noida, Kolkata & Chennai)

Engineer : 3+ Years

Job Description

Skill Set Requirements:

  • Full-chip DFT working experience with multiple design Tape Outs
  • Block level and Chip level SCAN insertion, DRC, Coverage Analysis and improvements.
  • Expertise in Scan Compression(EDT/OPMISR+), MBIST, BSCAN, ATPG implementation and verification.
  • Hands on Experience with industry standard DFT EDA tools & flows(Tessent,Synopsys,Cadence)
  • Good Knowledge of cross functional domains (SYN, LEC, STA, PD) with owner ship of constraints developments & LEC.
  • Excellent problem solving and debugging skills. Proactive in nature.
  • Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process
  • Leading junior teams, Mentoring/Training and Project leadership.
  • Excellent Customer interaction, Communication and Team work skills

Skills & Experience

ATPG (at-speed & stuck-at), Automatic Test Pattern Generation (ATPG), Design for Testability (DFT), Design Rule Checking (DRC), Formal Verification, Gate Level Simulation, Hardware Description Language (HDL), Test Pattern Generators.





Job Classification

Industry: Electronic Components / Semiconductors
Functional Area:
Role Category: Engineering & Manufacturing
Role: Engineering & Manufacturing
Employement Type: Full time

Education

Under Graduation: Any Graduate
Post Graduation: Any Postgraduate
Doctorate: Any Doctorate

Contact Details:

Company: Cyient Limited
Location(s): Hyderabad

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Keyskills:   dft Atpg Bist Mbist JTAG scan insertion

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Cyient

At Cyient, we work towards improving the daily lives of people with unwavering focus. From a quieter flight to a safer train journey, a more reliable energy supply, or a faster internet connection, we provide engineering, manufacturing, geospatial, network and operations management services to indus...