Vlsi Design Engineer
- Freelancer Akshay
- 5 to 10 Yrs
- Bengaluru
- 4 years ago
- Email to a friend
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Job Description
Job Description :-
Senior Verification Lead
Experience: 5-10 years or more
Location: Bangalore
Job Description:
- Experience in Industry standard protocols ARM Interconnects(AHB, APB), SPI, UART, I2C, DMA, Serial Flash, Security and Encryption.
- Full chip SoC (C and SV based), Subsystem and Block/IP level verification. Test Bench generation with ability to run embedded C programs. Must have experience of 2-3 SoC verification.
- Experience in HDL(Verilog, VHDL) and HVL(System Verilog, Specman) based functional verification. Experience in code coverage.
- Experience in Verification methodologies(UVM, OVM and eRM).
5.Mixed language simulation (Verilog-AMS, SystemVerilog).
- Experience in Mentor, Cadence and Synopsys simulators.
- Build automated Test bench and regression environments from a scratch. Should be able to write a test plan and generate test cases
- Regression management and Verification Sign-off based on Functional Verification and Code Coverage.
- Gate Level Simulation.
- Generation of Bus Functional Models, Protocol monitors and checkers.
- Power simulations using CPF/UPF.
Experience :-
- 5 yrs to 10 yrs of experience as Embedded / VLSI / ASIC / Chip Design in IT- Software mandatory
- Experience in HDL(Verilog, VHDL) and HVL(System Verilog, Specman) based functional verification. Experience in code overage.
- Full chip SoC (C and SV based), Subsystem and Block/IP level verification. Test Bench generation with ability to run embedded C programs. Must have experience of 2-3 SoC verification.
- Experience in Industry standard protocols ARM Interconnects(AHB, APB), SPI, UART, I2C, DMA, Serial Flash, Security and Encryption
- Experience in Mentor, Cadence and Synopsys simulators.
- Experience in Verification methodologies(UVM, OVM and eRM).
Others : -
- Generation of Bus Functional Models, Protocol monitors and checkers.
- Power simulations using CPF/UPF.
- Build automated Test bench and regression environments from a scratch. Should be able to write a test plan and generate test cases
- Experience in Mentor, Cadence and Synopsys simulators.
- Mixed language simulation (Verilog-AMS, SystemVerilog).
- Experience in Verification methodologies(UVM, OVM and eRM).
- Experience in HDL(Verilog, VHDL) and HVL(System Verilog, Specman) based functional verification. Experience in code coverage.
- Full chip SoC (C and SV based), Subsystem and Block/IP level verification. Test Bench generation with ability to run embedded C programs. Must have experience of 2-3 SoC verification.
- Experience in Industry standard protocols ARM Interconnects(AHB, APB), SPI, UART, I2C, DMA, Serial Flash, Security and Encryption.
Shift Timings
10:00 am - 7:00 pm(day shift)Weekly Working Days
5 Days
Off Days:
SAT,SUN. for more details,
contact to the below number,HR Akshay :- 6362045***.
Employement Category:
Employement Type: Full timeIndustry: IT - Hardware / Networking
Role Category: Embedded / System Software
Functional Area: Not Applicable
Role/Responsibilies: Vlsi Design Engineer
Contact Details:
Company: Shree SaiLocation(s): Bengaluru
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₹ 6 - 14 Lakh/Yr
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