Verification Engineers/Sr. Engineers/Lead/Manager : DV @ Koral Human Resource

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Verification Engineers/Sr. Engineers/Lead/Manager : DV

Koral Human Resource
3 - 13 Years
Bengaluru
4 years ago
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Job Description

Job Description
Masters/ Bachelors in EE/EC/CS with 4-10 years of experience in IP/SoC/ASIC Verification.
Experience with System Verilog and UVM. Develop verification IP which can be reused at different levels of verification: block level, sub-system level, SoC level, etc
Candidates are expected to have designed and developed UVM, SVTB and have previously composed functional coverage and assertions, preferably using System Verilog.
Knowledge in Networking domain like Ethernet, Cryptography protocols etc - an advantage
Expertise in Scripting languages like Perl/Python
Excellent communication, problem solving and analytical skills

Employement Category:

Employement Type: Full time
Industry: Semiconductor
Functional Area: IT- Hardware
Role Category: Verification Engineer
Role/Responsibilies: Verification Engineers/Sr. Engineers/Lead/Manager : DV

Contact Details:

Company: Koral Human Resource
Location(s): Bengaluru

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Koral Human Resource

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Verification Engineers/Sr. Engineers/Lead/Manager : DV @ Koral Human Resource

Home > Verification Engineer