Software Engineer II (Formal Verification IP)
- Cadence Design Systems
- 4 - 8 years
- Noida, Gurugram
- 3 years ago
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Job Description
Minimum Qualifications:
Bachelors Degree+1 or more years industry experience or Masters Degree+internship experience as a RTL Design and/or Verification Engineer.
Position Requirements:
- Very good understanding of HDLs (Verilog, System Verilog) and System Verilog Assertions is MUST
- Knowledge of at least one industry standard protocol (for example AHB, AXI, CHI, PCIe etc) is a MUST
- Very strong RTL design and synthesis concepts is required
- Strong verification concepts like understanding spec, creating test plans, adding coverage is required
- Strong analytical and problem solving skills required
- Formal verification knowledge will be a plus
- Experience in process automation with Python/TCL scripting will be a plus
- He/she should have a good working knowledge of EDA tools (Cadence/ Others) with focus towards debugging design/verification problems using these tools.
- He/she should have good communication skills.
Job Classification
Industry: Software ProductFunctional Area: Engineering - Software & QA,
Role Category: Software Development
Role: Software Development
Employement Type: Full time
Education
Under Graduation: Any GraduatePost Graduation: Any Postgraduate
Doctorate: Doctorate Not Required, Any Doctorate
Contact Details:
Company: Cadence Design SystemsLocation(s): Noida, Gurugram
Keyskills: Process automation formal verification Analytical Debugging System design HTML System verilog PCIE IPS Python
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Cadence is a leading provider of EDA and semiconductor IP. Our custom/analog tools help engineers design the transistors, standard cells, and IP blocks that make up SoCs. Our digital tools automate the design and verification of giga-scale, giga-hertz SoCs at the latest semico...
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