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Principal Design Engineer - Pune - Cadence @ Cadence Design Systems

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 Principal Design Engineer - Pune - Cadence

Job Description

  • RTL coding and micro-architecture of complex RTL design blocks for high performance design.
  • You will run lint, synthesis on the RTL design block to ensure high quality RTL which can meet timings at 1GHz + frequencies.
  • You will support the Design verification team in debug and fix RTL issues in the blocks.
  • You will help in identifying corner conditions and developing assertions for the RTL blocks to facilitate verification.

Required Skills

  • Writing RTL for state machines and controllers for DMA operations.
  • Writing Logic for interfacing to complex memory subsystems with multiple banks and read/write ports and optimizing design for low latency and high bandwidth data transfers.
  • Experience in design of logic for supporting on chip interfaces like AXI-4.
  • Developing logic for control of registers/register files and logic supporting debug paths for CSR/memory read/write, profiling monitors.
  • Experienced in full chip integration of RTL blocks

Job Classification

Industry: Software Product
Functional Area: Engineering - Software & QA,
Role Category: Software Development
Role: Software Development
Employement Type: Full time

Education

Under Graduation: Any Graduate
Post Graduation: Any Postgraduate
Doctorate: Doctorate Not Required

Contact Details:

Company: Cadence Design Systems
Location(s): Pune

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Keyskills:   Design verification RTL design CSR Architecture RTL coding Debugging Banking Dma RTL Principal

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Cadence Design Systems

Cadence is a leading provider of EDA and semiconductor IP. Our custom/analog tools help engineers design the transistors, standard cells, and IP blocks that make up SoCs. Our digital tools automate the design and verification of giga-scale, giga-hertz SoCs at the latest semico...