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Lead DDR Release Engineer @ Cadence Design Systems

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 Lead DDR Release Engineer

Job Description

Essential Qualifications :

  • College education in Electrical Engineering or Computer Engineering
  • Strong knowledge (and experience) of scripting languages (Perl, TCL, Python)
  • Abilities to follow complex code execution, detect code errors, debug and make necessary fixes.
  • Working knowledge of Verilog, synthesis, static timing analysis, logic equivalence check
  • Ability to debug existing Verilog test cases with little or no help from the designer.
  • Ability to develop/debug synthesis/timing analysis constraints, reports, logs
  • Ability to learn new tools/flows and develop methodology if needed.
  • Strong interpersonal, and relationship-building skills.
  • Ability to build and maintain close relationships with Designers and Application Engineers.
  •  Fastidious approach to building automated processes
  • Time management skills enough to balance multiple high-priority projects.

Additional Desirable Qualifications :

  • Familiarity with DDR memory operation, system applications, AMBA protocols
  • Familiarity with Power Flow (UPF/CPF)
  • Familiarity with FrameMaker

Job Classification

Industry: Software Product
Functional Area: Research & Development,
Role Category: Engineering & Manufacturing
Role: Engineering & Manufacturing
Employement Type: Full time

Education

Under Graduation: B.Tech/B.E. in Production/Industrial
Post Graduation: M.Tech in Electronics/Telecommunication
Doctorate: Any Doctorate

Contact Details:

Company: Cadence Design Systems
Location(s): Bengaluru

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Keyskills:   Electrical engineering static timing analysis Operating systems Time management Relationship building Verilog Debugging Perl Test cases Python

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Cadence Design Systems

Cadence is a leading provider of EDA and semiconductor IP. Our custom/analog tools help engineers design the transistors, standard cells, and IP blocks that make up SoCs. Our digital tools automate the design and verification of giga-scale, giga-hertz SoCs at the latest semico...