Design Engineer II - Pune - Cadence Design @ Cadence Design Systems

Responsibilities:

• As a member of the Design Verification Team for Xtensa processors you will be responsible for verification of microprocessor cores and their peripherals.
• You will implement simulation or emulation testbenches, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals.
• You will also assist with developing testplans, debugging failures and analyzing coverage information.
• You will work closely with the RTL and EDA teams.

Required Skills and Experience:

• MTech (or higher) in EE/Computer Engineering
• Prior Job Experience (1-3 yrs) in Design Verification is preferred.
• Excellent knowledge of computer architecture and design verification fundamentals
• Some experience with Verilog and popular EDA simulation, System Verilog assertions and testbench methodologies
• Knowledge of SystemVerilog and UVM methodology
• Exposure to scripting languages like Perl, Unix shell or similar languages
• Experience with assembly language programming is a plus
• Excellent written and oral communication skills
• Candidate must be self-motivated and capable of working independently or as part of a team
• Knowledge of Formal Verification will be a plus