FEV and Low Power Verification Engineer
- Intel
- 5 - 6 years
- Bengaluru
- 2 years ago
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Job Description
- As an integral part of Intels new IDM2.0 strategy, we are establishing Intel Foundry Services (IFS), a fully vertical, standalone foundry business.. IFS will be a world-class foundry business and major provider of US and European-based capacity to serve customers globally. Intel Foundry Services will be differentiated from other Foundry offerings with a combination of leading-edge packaging and process technology, committed capacity in the US and Europe - available for customers globally
- - and a world-class IP portfolio that customers can chose from including x86 cores, graphics, media, display, AI, interconnect, fabric and other critical foundational IP, along with ARM and RISC-V ecosystem IPs. IFS will also provide access to silicon design services to help our customers seamlessly turn silicon into solutions, using industry standard design packages. This business unit is completely dedicated to the success of its customers with full P and L responsibilities.
- This model will ensure that our foundry customers products will receive our utmost focus in terms of service, technology enablement and capacity commitments.
- IFS is already engaged with customers today starting with our existing foundry offerings and we are expanding imminently to include our most advanced technologies, which are optimized for cutting-edge performance, making them ideal for high-performance applications.
- We are looking for experienced SoC Design Engineer to drive the low power signoff and FEV closure of the high performance and automotive SoCs. Responsibilities include setting up the signoff requirements for low power static checks and formal equivalence verification integrated into the signoff flows, driving the convergence of the blocks by working with the partition owners, owning and closing the Fullchip signoff for low power static verification and FEV and reporting out the status of the convergence using appropriate indicators.
- He / She should have in-depth experience in VCLP, Conformal-LP, LEC, Formality or equivalent signoff tools in this domain. He/she should be an expert in the low power design techniques and hands on experience in writing or updating the IEEE 1801 UPF constructs used for low power implementation and signoff. He/she should have good understanding of equivalence checks and hands-on expertise in debugging FEV failures on complex datapath designs. Teamwork / flexibility / ability to thrive in a dynamic environment are very important.
- Qualification: 10 Years of relevant Experience after a Bachelor or Master of Engineering degree in Electrical/ Electronic/VLSI Engineering or related field.
- Good Expertise in low power static and FEV signoff at subsystem level and SoC level is required.
Job Classification
Industry: Electronic Components / SemiconductorsFunctional Area: Engineering - Software,
Role Category: Software Development
Role: Software Development
Employement Type: Full time
Education
Under Graduation: Any GraduatePost Graduation: M.Tech in Electronics/Telecommunication
Contact Details:
Company: IntelLocation(s): Bengaluru
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Keyskills: Graphics VLSI SOC Debugging X86 IFS Silicon IPS Automotive IEEE
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