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Soc Design Verification Engineer @ Intel

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 Soc Design Verification Engineer

Job Description

  • The candidate will work as a member of a verification team, playing a key/leading role in developing Ethernet Network Interface Controller products.

The Responsibilities will Include but not be limited to:

  • Create/contribute to verification test plans
  • Understand the architecture and design of the verification environment in OVM/UVM and create components used by test environment
  • Develop/run/debug tests and functional coverage in SystemVerilog
  • Ownership of verification of block/cluster level testing or a significant feature set in a chip/subsystem level testing
  • Participate in code review process and provide/implement feedback
  • Participate in func coverage, code coverage reviews and provide/implement feedback
  • Able to use automation and productivity tools to maximize impact on overall schedule
  • Track progress to achieve goals timely
  • Contribute to the development and maintenance of long term design verification strategy
  • Be able to work with teams across geos


  • B.Tech 3-6 yrs or M.Tech 2-5 yrs domain experience out of which 2 years of hands-on verification experience using SystemVerilog and OVM/UVM
  • Strong understanding of engineering design principles
  • Proficiency in SV, OVM, UVM a

Job Classification

Industry: Electronic Components / Semiconductors
Functional Area: Engineering - Software,
Role Category: Software Development
Role: Software Development
Employement Type: Full time

Education

Under Graduation: B.Tech/B.E. in Production/Industrial
Post Graduation: M.Tech in Electronics/Telecommunication
Doctorate: Any Doctorate

Contact Details:

Company: Intel
Location(s): Bengaluru

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Keyskills:   Automation Simulation SOC Ethernet Perl Engineering Design SCM UVM Object oriented programming Python

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