Senior ASIC Physical Design Engineer
- Intel
- 7 - 12 years
- Bengaluru
- 4 years ago
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Job Description
- IPG APAC is seeking an ASIC Timing Signoff Design Engineer to join our talented and vibrant team.
- You will be directly involved in delivering next-generation LPDDR5 / DDR5 PHY or Die2Die Interconnects PHY designs for SOC application on leading process nodes.
Key Responsibilities for this position includes but not limited to:
- Technical know-how of RTL to GDSII phase of the ASIC design flow with expert-level understanding and hands-on experience of constraints development, timing analysis and signoff closure
- Expert-level understanding and generation of Constraint/exceptions, clock definitions, IP timing analysis and signoff, IP lib modeling, timing signoff methodology and multi
- PVT timing convergence and signoff.
- Knowledge of advanced signoff analysis concepts such as multi-power domain analysis, POCV, spatial analysis is good to have.
- Having hands-on experience of Synthesis, formal equivalence, CTS, place and route, physical layout verification is a plus.
- You should possess a relevant educational qualification, BSEE or equivalent with 7 years/MSEE or equivalent with 5 years design experience in the timing/physical design domain.
Additional qualifications include:Have multiple tap
Job Classification
Industry: Electronic Components / SemiconductorsFunctional Area: Engineering - Software, Role Category: Software DevelopmentRole: Software DevelopmentEmployement Type: Full timeEducation
Under Graduation: Any GraduatePost Graduation: Any PostgraduateDoctorate: Any DoctorateContact Details:
Company: IntelLocation(s): Bengaluru+ View Contact
Keyskills: VLSI static timing analysis Architecture EDA tools SOC Perl ASIC Design Internship Python Physical design
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