Silicon Engineering of Intels Ethernet Product Group is looking for Structural and Physical Design engineers to build Ethernet Network Interface Controller IP and SOCs. The selected candidate will be joining its India team and work on IP/subsystem/full chip level physical design tasks spanning from RTL synthesis to final sign-off.
Role in question is for block level physical design engineer who would be responsible for end-to-end physical implementation of one or more blocks starting from RTL synthesis, floorplanning, clock tree synthesis, timing and physical convergence.

Keyskills: Backend static timing analysis EDA tools SOC Ethernet Electronics Silicon VLSI design Floor planning Physical design
Our Client is a mid level web and mobile application development company located at Kovilambakkam.