Soc Synthesis Fev And Sta Convergence Engineer
- Intel
- 6 - 8 years
- Bengaluru
- 4 years ago
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Job Description
We are a team developing Test Chip and SOC for critical IPs at Intel. All test chips will go through Concept to Design to Tape-IN. Team also support post silicon team in power on enablement.
All IPs will be silicon tested using our test vehicle.
We also implement cutting edge SOC for new architectures for proof of concept before intercepting product SOC. This position is to support RTL to Netlist and Timing Convergence.
Candidate should be able to support synthesis of RTL and generate netlist, which will be delivered to Physical design team for implementation.
Candidate will also work with Design Enabling team (TFM - tools flows and methodology team) to come up with flow for netlist creation, generate synthesis netlist for SOC. Should be able to work with partition owners in generation of netlist using the flow. Candidate will own STA for Full Chip.
Candidate should generate FC timing ECOs and work with Partition Physical Design Engineers for full chip timing convergence.
Candidate with FEV background will be considered with preference.
Candidate should be able to work with junior engineers working on the same domain.
Minimum Experience of the candidate should be 6 to 8 years. Higher experienced candidate may also apply with a better position and pay package. Minimum Qualifications:
Bachelors of Engineering in ECE, CSE, EEE Preferred Qualifica
Job Classification
Industry: Electronic Components / SemiconductorsFunctional Area: Engineering - Software, Role Category: DBA / Data warehousingRole: DBA / Data warehousingEmployement Type: Full timeEducation
Under Graduation: B.Tech/B.E. in Production/IndustrialPost Graduation: Any PostgraduateDoctorate: Any DoctorateContact Details:
Company: IntelLocation(s): Bengaluru
Keyskills: STA VLSI SOC Team development Silicon RTL IPS Physical design Testing
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