Develops preSilicon functional validation tests to verify system will meet design requirements.
Creates test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests.
Analyzes and uses results to modify testing.Candidates need to have extensive experience and proven capabilities in defining SOC / SS level Validation Strategy, Understanding SOC Architecture, Product level Use-cases, Driving Test Plan definition, Implementing TB components, coding sequences, checkers, assertions, coverage, and debugging RTL/GLS/Emulation tests.
Candidates should possess extensive knowledge of System Verilog, SVA, OVM and/or UVM methodology, and driving Code and Functional coverage closure.
Knowledge of C, , Formal Verification techniques, Interface protocols is a must.
Candidate will develop new test bench methodologies to improve metric based overall simulation efficiency.Candidates should have the ability to work effectively with both internal and external teams and stakeholders.
Strong problem solving and communication skills are desired.
Candidates should be good team player, mentor junior validation engineers and be able to influence various program stakeholders across Architecture, Design, and SW.
QualificationsBachelors or Masters degree in Electrical, Electronics or Computer Engineering with 15years of relevant industry in pre-Si Validation domain
Relevant ASIC design/validation experience in front end processes including SOC level R

Keyskills: Graphics Front end Networking Coding SOC Debugging Test planning System verilog Firmware IPS
Our Client is a mid level web and mobile application development company located at Kovilambakkam.