STA Lead Engineer / Senior Engineer
- Mulya Consulting
- 7 - 12 years
- Hyderabad
- 2 years ago
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Job Description
STA Lead Engineer / Senior Engineer
Top2 Semiconductor Organization in the world
Location: Bangalore / Hyderabad
Job Description:
As an integral part of our new strategy, we are establishing Foundry Services , a fully vertical, standalone foundry business, . we will be a world-class foundry business and major provider of US and European-based capacity to serve customers globally. Our Services will be differentiated from other Foundry offerings with a combination of leading-edge packaging and process technology, committed capacity in the US and Europe - available for customers globally - and a world-class IP portfolio that customers can chose from including x86 cores, graphics, media, display, AI, interconnect, fabric and other critical foundational IP, along with ARM and RISC-V ecosystem IPs. we will also provide access to silicon design services to help our customers seamlessly turn silicon into solutions, using industry standard design packages. This business unit is completely dedicated to the success of its customers with full P and L responsibilities. This model will ensure that our foundry customers' products will receive our utmost focus in terms of service, technology enablement and capacity commitments. we are already engaged with customers today starting with our existing foundry offerings and we are expanding imminently to include our most advanced technologies, which are optimized for cutting-edge performance, making them ideal for high-performance applications.
Position Description
The timing sign-off lead's responsibilities include Definition/Development of constraints for SOC Sign-off, setting up Timing Analysis Environment, driving timing convergence through influence of APR, Producing timing indicators to track the execution progress and final tape-out quality Sign-off .
He / She should have in-depth experience in Primetime or equivalent tool-based Timing Analysis and should be an expert in developing SDC constraints, setting up Fullchip or subsystem level timing environment, Automating the Timing Execution/Indicator Extraction. He/She should have solid understanding of SOC Clocking Methodology, Understanding of requirements for Clock Domain Crossing, Clock Balancing across SOC partitions, Subsystem Level Logical/Physical Partitioning, implication of partitioning on overall Design Convergence. In addition, She/he must be able to influence RTL, APR execution and floor planning.
Qualifications
7-15 Years of relevant Experience After a Bachelor or Master of Engineering degree in Electrical/ Electronic/VLSI Engineering or related field.
Must have led at least 2 SOCs in capacity of SOC Sign-off lead especially on Sub 7nm projects.
Solid Expertise in Primetime or Similar timing tools and good understanding of overall ASIC Physical Design/DFT, Tools and implication on Timing Convergence
Must have in-depth understanding of relevant areas of Library / Memory / Other collaterals and dependencies on STA
Must understand Ultra Submicron issues, Variation aware/Aging Aware Design Sign-off
Must understand CTS/Other clock Distribution methodologies well.
Teamwork / flexibility / ability to thrive in a chaotic environment are very important
Experienced Hire
Primary Location:
India, Bangalore
Contact: Uday Bhaskar
Mulya Technologies
"Mining the Knowledge Community"
Email id : mu**********r@ya**o.com
Job Classification
Industry: Electronic Components / SemiconductorsFunctional Area: Engineering - Hardware & Networks,
Role Category: Hardware
Role: Hardware
Employement Type: Full time
Education
Under Graduation: B.Tech/B.E. in Any SpecializationPost Graduation: MS/M.Sc(Science) in Any Specialization, M.Tech in Any Specialization
Doctorate: Any Doctorate, Doctorate Not Required
Contact Details:
Company: Mulya ConsultingLocation(s): Hyderabad
Keyskills: STA cts Cdc sign-off time constraints tempus sdc constraints Primetime clocking Timing Closure timing constraints timing convergence budget constraints Physical Design Timing
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