Senior SOC Design Engineer
Top2 Semiconductor Organization in the world
Location : Bangalore
Job Description
. As a member of the SOC-FPGA Configuration design team, you will be responsible for the micro-architecture, RTL design and/or integration of SoC components and IPs. Core responsibilities will include:
- Work with architects, software engineers, verification engineers and physical designers to define and implement the logic for our unique SOC-FPGA products, within a culture of industry standard best practices and methodologies. - Designing and writing well-documented, high quality and synthesis-friendly RTL.
- Working with the Design Verification team to review test plans and assist in test failure debug. - Support the post-silicon validation team to define validation strategies, test plans, quality reviews and assist with debug when necessary.
- Defining timing constraints and working with physical design engineers for design implementation.
Qualifications
The successful candidate's minimum qualifications will include the following: - BSEE or MSEE with 7+ years of relevant experience,
- Proven industry-track in writing and verifying complex RTL logic for SOC designs, preferably in Verilog or System Verilog.
- Experience working with verification engineers on simulation or emulation flows and familiarity with industry standard verification methodologies (UVM, assertions etc). - Experience working with physical design engineers to assist with the implementation flow, eg clock tree synthesis, floor planning and implementing ECO fixes.
- Strong analytical and communication skills and be able to work with and influence a globally distributed team. - Familiarity with designing/integrating cryptographic, interface, storage and/or compression IPs will be a plus.
- Experience in low-power designs SoC will be a plus.
Contact: Uday Bhaskar
Mulya Technologies
"Mining the Knowledge Community"
Email id : mu**********r@ya**o.com
Keyskills: ip integration rtl design Storage microarchitecture soc design cryptography RTL Coding compression soc integration System Verilog UVM verilog
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