We are looking for someone who has passion around improving the way we solve complex problems through team work as well as their own direct contributions.
Direct Responsibilities:
In this role you will be responsible for working with stakeholders to implement and verify DFT features in pre silicon as well as supporting silicon validation for leading edge SoC designs.
Includes responsibility for supporting manufacturing and testability of our products, design; verification using Scan ATPG tools for pattern generation and coverage, debug, scan synthesis, Test Mode STA and gate level simulation.
Also includes experience in MBIST, JTAG ( 1149.1, 1149.6 ; 1149.7) , IJTAG ( 1687), BScan design implementation and verification.
Responsibilities include delivery of high-quality documentation for consumption by the post-silicon teams using the DFx features.
The ideal candidate will be able to demonstrate the following behaviors: Ability to work effectively with both internal and external teams/customers.
Ability to mentor other engineers and technically guide them.
Strong problem-solving skills. Strong written and verbal communication skills.
Facilitator of direct and open communication, diversity of opinion, and debate.
BS degree in Electrical Engineering Computer Engineering or other related field of study with a minimum of 14 years or MS degree with 12 years of directly related industry experience in SOCIP DFx Design and Verification.
Candidates must have

Keyskills: JTAG Timing closure DFT Simulation SOC Shell scripting atpg Perl System verilog Physical design
Our Client is a mid level web and mobile application development company located at Kovilambakkam.