Energetic and passionate senior Logic Design Engineers to develop high speed Serdes(like PCIe, Ethernet, MIPI CPHY/DPHY/MPHY/APHY etc)
Person should be able to independently work & develop various logic design and development activities including micro-architecture, RTL code from high level specs, ensure end to end design quality in terms of Lint / CDC / DFT / Synthesis / STA / Formal Equivalence etc.
Hands on prior experience of developing and working similar high speed Serdes with multiple clock domain, power plan designs
You would be expected to develop micro-arch of the block/IP you own and also participates in the various Architecture and Microarchitecture specifications forums the Logic components.
Provides IP integration support to SoC customers and represents RTL/logic design team.
As design owner, you would also be expected to review and drive test plan, assertions and overall quality of the block/IP.
You should be able to interact with various stake holders (internal as well as external) to drive end 2 end quality, design objectives within stipulated schedule timelines.
Familiarity with overall silicon development cycle from concept to PRQ including DFT/DFD/Post Silicon debug support, HW/SW partitioning is desired.
Expertise with Verilog, system Verilog, C, C , Perl languages
Ability to clearly express technical concepts in verbal and written form
Innovative thinking, problem solving, good communication skills, self-discipline and results orientation are critical soft-skills needed
Good hands-on knowledge on industry standard EDA tools & HDLs
Must be a extremely good team player and should be able to work across organization boundaries and domains

Keyskills: DFT VLSI Architecture SOC Ethernet Test planning Perl System verilog PCIE IPS
Our Client is a mid level web and mobile application development company located at Kovilambakkam.