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Intern-Product Engineering @ Cadence Design Systems

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 Intern-Product Engineering

Job Description


Job Description :
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence Design Systems is seeking a highly motivated graduate student for internship in the Product Engineering team. The Cadence Digital and Signoff Group will offer you a dynamic environment in which you will work with innovative R&D and Customer Engagement teams to influence the development of software tools for advanced chip design platforms.
Position Responsibilities
  • Supporting customers on Cadence Quantus Parasitic Extraction tool
  • Designing, developing, troubleshooting and debugging software programs on Unix/Linux platforms
  • Supporting Customers in performing successful tapeouts of their System-on-chip designs

The Position Requirements are
Position Requirements
  • Currently enrolled in MS studies in Computer Science or Electrical Engineering
  • Experience with EDA tools and with VLSI design familiar with digital implementation challenges including clock tree synthesis, routing, optimization and silicon signoff.
  • Understanding of Parasitic Extraction and its role in full flow
  • Experience with UNIX and/or LINUX platforms
  • Strong knowledge of Perl/Tcl
  • Strong analysis and problem solving skills
  • Excellent algorithmic skills
  • Team Player
  • Strong ability and passion to learn
  • Excellent verbal and written communication skills
We're doing work that matters. Help us solve what others can't.

Employement Category:

Employement Type: Full time
Industry: IT
Functional Area: IT
Role Category: Software Engineer
Role/Responsibilies: Intern-Product Engineering

Contact Details:

Company: Cadence Design Systems
Location(s): Noida, Gurugram

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Cadence Design Systems

Cadence is a leading provider of EDA and semiconductor IP. Our custom/analog tools help engineers design the transistors, standard cells, and IP blocks that make up SoCs. Our digital tools automate the design and verification of giga-scale, giga-hertz SoCs at the latest semico...