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Principal Design Engineer @ Cadence Design Systems

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 Principal Design Engineer

Job Description


Job Description :
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Description:

  • In charge of DDR IP logic design implementation, including SDC development, logic synthesis, logic equivalence check

  • Co-work with FE team to do the quality check for DDR IP, make sure RTL/SDC/synthesis netlist released to customer successfully

  • Co-work with internal PD team for DDR IP timing closure issue

  • Support on customer for DDR IP integration issue related to STA part

Job Requirements:
1. Strong Static Timing Analysis skill.
2. Understand logic synthesis, sta analysis, logic equivalence check, familiar with EDA tool usage for synthesis/sta analysis/lec check flow
3. Basic knowledge about digital logic design and HDL language Knowledge, like verilog or vhdl is necessary.
4. perl/tcl/csh, UNIX, Linux experience are plus.
5. Excellent analytical and problem-solving skills. Quick learner-able to learn and apply technical and complex topics.
6. Excellent communication skills and the uncanny ability in a cooperative team environment are required.
7. Self-motivated, result-oriented, can take ownership and follow-through on tasks.We're doing work that matters. Help us solve what others can't.

Employement Category:

Employement Type: Full time
Industry: IT
Functional Area: IT
Role Category: Hardware Design Engineer
Role/Responsibilies: Principal Design Engineer

Contact Details:

Company: Cadence Design Systems
Location(s): Noida, Gurugram

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Cadence Design Systems

Cadence is a leading provider of EDA and semiconductor IP. Our custom/analog tools help engineers design the transistors, standard cells, and IP blocks that make up SoCs. Our digital tools automate the design and verification of giga-scale, giga-hertz SoCs at the latest semico...