4 positions
IP Verification- Senior Engineers
Location : Hyderabad / Bangalore (First 8 months remote)
We are emerging as a Top class leading semiconductor engineering solution provider. We always offer our customers the services which is the right solution for their tasks, whether it is a chip which is customized to their requirements (ASIC),
Required to work on IP / Subsystem level verification and own various DV tasks from Test plan creation, coverage model development, test case writing and coverage closure.
Skills: UVM, SV, SVA (assertions)
Expected to do full triaging in collaboration with design team and proactively report status of progress
Should be proficient in System-Verilog and scripting language like Shell, Perl . Must have RTL/gate level simulation debug experience. Should have a working knowledge of bus protocols like AHB/AXI . candidates should have 3-6 years experience.
Contact: Uday Bhaskar
ud*********r@sm******s.com

Keyskills: ASIC Ddr c Sv ASIC Verification Amba SOC ARM System Verilog UVM gls sva
We are emerging as a Top class leading semiconductor engineering solution provider. We always offer our customers the services which is the right solution for their tasks, whether it is a chip which is customized to their requirements (ASIC),