Location: Bangalore
Job Responsibilities:
Digital Design/RTL Implementation
Synthesis, Static Timing Analysis, Power analysis.
Position Requirements
- BTech/MTech degree in Electrical/Electronics with 2-10 years of experience
Experience in few of the below areas are required:
- RTL Design, Power analysis, LINT cleaning, CDC
- Strong expertise in Static Timing analysis , constraint development and sign off.- Floor Planning, Power Plan, Place and Route, Clock Planning and Clock Tree Synthesis, Parasitic Extraction-Innovate on the flows to meet the QoR targets and ensure predictability
- Good understanding on device/interconnect and circuit aspect of the complex UDSM technologies is an added advantage.
Uday
Mulya Technologies
"Mining the Knowledge Community"
Email id : mu**********r@ya**o.com

Keyskills: CDC place and route SOC Lint parasitic extraction power plan rtl development Power Analysis verilog ASIC Floor Planning qor microarchitecture soc design Static Timing Analysis RTL Coding ASIC Design Clock Tree Synthesis System Verilog RTL Design logic design
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