Principal Dft Engineer
- Mulya Consulting
- 10 - 20 years
- Hyderabad
- 5 years ago
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Job Description
- Principal DFT Engineer
- Location :Bangalore / Hyderabad
- This position is a permanent position with our client (US Based Semiconductor Product Company with revenue more than 30 Billion USD)
- Our client is a world leader (Top5 Semicon Company in 2018) in innovative memory solutions that transform how the world uses information. They have over 34,000 team members in 17 countries who work with the worlds most trusted brands, delivering memory and storage systems for a broad range of applications and sparking countless possibilities in technology
As an experienced DFT engineer , you will be involved with DFT implementation of SoCs.
Successful Candidate will be responsible for architecture/implementation of DFT for zero DPPM GHz SoCs in sub-16nm technology nodes
The engineer will be one point of contact for delivery of test vectors, Scan mode timing closure, and will be front line engineer during product qual.
You will work with a creative and highly motivated design team using state of the art memory technologies.
Successful candidates for this position should have :
- Exposure to different scan architectures & implementation of such for SoCs.
- Must have functional & integration knowledge of TAP controllers and JTAG.
- Hands-on experience with boundary-scan insertion, generation, simulation , including knowledge of memory bist/bisr/bihr
- Must be well aware of scan compression and test time reduction
- Must have basic idea of MBIST algorithms
- Must know how to write constraints for DFT modes
- Must know how to merge timing modes/mode reduction in collaboration with STA
- Has prior experience interfacing ATE requirements, tester hand-off languages/TDL/WIGL/STIL/BSDL and must know to drive/modify test procedures.
- Should have worked directly to close STA in DFT modes.
- It is highly desirable that candidate should be able to come up with an implementation plan independently given a test plan.
Minimum Qualifications:
- Bachelors of Engineering in E&C/Electrical/Computer Science
- A minimum with 10-15 years of physical design experiences Exclusively in DFT
- A deep understanding of DFT flows for SCAN/MBIST/BSCAN
- Proficient in writing SDC constructs for DFT modes
- Proficient with EDA tools from Synopsys/Cadence/Mentor Graphics
- Proficiency in Tcl and Perl
- Excellent analytical skills
- Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone
Preferred Skills:
- Strong interpersonal skills both written and verbal
- You are ambitious, goal-oriented, and dedicated
- Collaborate effectively in a dynamic environment
- Contact: Uday Bhaskar
- Mulya Technologies
- "Mining the Knowledge Community"
- Email id : mu**********r@ya**o.com
Job Classification
Industry: Semiconductors, ElectronicsFunctional Area: IT Software - Embedded, EDA, VLSI, ASIC, Chip Design, Role Category: Programming & DesignRole: Programming & DesignEmployement Type: Full timeEducation
Under Graduation: B.Tech/B.E. in Any SpecializationPost Graduation: M.Tech in Any Specialization, MS/M.Sc(Science) in Any SpecializationDoctorate: Doctorate Not Required, Any Doctorate in Any SpecializationContact Details:
Company: Mulya ConsultingLocation(s): Hyderabad
Keyskills: DFT testmax bscan Cadence tessent Modus dft architecture JTAG Atpg tetramax Bist Mentor Graphics mbist Synopsys
Mulya Consulting
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