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Senior Design Verification Engineers (UVM +) @ Mulya Consulting

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 Senior Design Verification Engineers (UVM +)

Job Description

Senior Design Verification Engineers / Lead

Client: Large Service Company in Semiconductors, part of MNC with revenue of Multi- Billion USD

Location: Bangalore / Pune / Noida / Ahmedabad

  • B.Tech/M.Tech in Electronics or Computer Science Engineering.
  • Minimum 4+ years of experience.
  • Minimum 3 to 6 years of experience in System Verilog HVL.
  • Minimum 2 to 5 years of experience in UVM.
  • Hands-on experience in developing assertion, checkers, coverage, and scenario creation.
  • Must have executed at-least 2 SoC Verification project
  • Experience in developing test and coverage plan, Verification environment, and validation plan.
  • Knowledge of at least one industry-standard protocols like Ethernet, PCIe, MIPI, USB or similar is required.
  • Expertise in IP as well as SOC verification
  • Perl / shell scripting is good to have

Qualifications:

B.E., B.TECH, M.E. M. TECH

Contact: Uday Bhaskar

Mulya Technologies

"Mining the Knowledge Community"

Email id : mu**********r@ya**o.com

Job Classification

Industry: Semiconductors, Electronics
Functional Area: IT Hardware, Technical Support, Telecom Engineering,
Role Category: IT Hardware
Role: IT Hardware
Employement Type: Full time

Education

Under Graduation: B.Tech/B.E. in Any Specialization
Post Graduation: MS/M.Sc(Science) in Any Specialization, M.Tech in Any Specialization
Doctorate: Doctorate Not Required, Any Doctorate in Any Specialization

Contact Details:

Company: Mulya Consulting
Location(s): Pune

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Keyskills:   System Verilog UVM Phy MIPI USB Ethernet OTN CSI PCIE DSI

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