RTl Design - Low Power Design
- Qualcomm
- 5 - 10 years
- Bengaluru
- 4 years ago
- Email to a friend
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Job Description
Key Responsibilities
Develop micro-architecture and RTL design for Cores related to Low Power. Responsible for block level design.
Micro architecture and enabling SW teams to use HW blocks.
Running ASIC development tools including Lint and CDC.
Report status and communicate progress against expectations.
5-to 10 years of work experience in ASIC/SoC Design
Experienced in RTL design using Verilog / System Verilog.
Knowledge and experience of defining HW/FW interfaces.
Experienced in Linting, CDC and LEC.
Experienced in database management flows with Clearcase/Clearquest.
Knowledge and experience of defining HW/FW interfaces.
Ability to program effectively in Verilog, C/C++, Python, Perl
Excellent oral and written communications skills
Proactive, creative, curious, motivated to learn and contribute with good collaboration skills..
Job Classification
Industry: Semiconductors, ElectronicsFunctional Area: Engineering Design, R&D,
Role Category: Engineering Design
Role: Engineering Design
Employement Type: Full time
Education
Under Graduation: Any Graduate in Any SpecializationPost Graduation: Post Graduation Not Required
Doctorate: Any Doctorate in Any Specialization
Contact Details:
Company: Qualcomm TechnologiesLocation(s): Bengaluru
Keyskills: RTL design C++ ASIC Digital design Staffing SOC Verilog Perl System verilog Python
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