Sr Design Engineering Manager
- Cadence Design
- 5 to 6 Yrs
- Bengaluru
- 5 years ago
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Job Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
High Speed Serdes Verification Lead
Strong background in mixed signal verification fundamentals, behavioral modelling, verification environment planning & development is a must.
Prior mixed signal verification experience in some of the serial bus protocol IP s (PHY: USB /PCIE/DDR/DPHY/MPHY)
Strong expertise in real number modelling using Verilog-AMS/SV.
Experience in PSL/SV assertions development
Strong RTL and GLS debug skills.
Expertise in more than one of following skills is an added plus:
Power-aware RTL set-up, simulation and debug
Formal verification.
Gate-level simulations ( unit-delay, with sdf for timing).
Some exposure to Automotive IP verification
Prior experience of technically leading team is desirable and an added advantage
Should be process oriented and have a passion for scripting/automation
Good soft skills and experience of working collaboratively in cross site environment.
We re doing work that matters. Help us solve what others can t.,
Employement Category:
Employement Type: Full timeIndustry: IT - Software
Role Category: Embedded / System Software
Functional Area: Not Applicable
Role/Responsibilies: Sr Design Engineering Manager
Contact Details:
Company Name: Cadence DesignLocation(s): Bengaluru
Keyskills: pcie phy sv ddr serdes ip rtl verilog ams gls cadenc
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