IC Design Engineer @ VMware

Candidate should have very good experience in Physical design activities of block and SoC level. Should be well experienced in floor-planning, partitioning, placement, clock tree synthesis, route , physical verification and all signoff checks closure.

Experience with tools such as Innovus/Encounter, ICC, Caliber, LEC, Primetime etc is highly desirable. Full chip tape out experience based on 5nm/7nm/16nm technologies is preferred.

Candidate would be required to work on various phases of SOC physical design activities of top level & block level - floor-planning, partitioning, placement, clock tree synthesis, route, physical verification (LVS/DRC/ERC/Antenna etc).

Should have excellent problem solving skill to help through congestion resolution and timing closure. Candidate should be able to meet congestion, timing and area metrics of design. Would be required to do equivalence checks, STA, Crosstalk delay analysis ,noise analysis, power optimization. Should be able to implement timing and functional ECOs.

In this role, the Engineer will apply Broadcoms proven design methodology and milestone flow to meet Broadcoms rigorous criteria for achieving Right-first time silicon.

Candidate should be able to work independently and guide other team members. Should be experienced in working in a global team and dynamic environment.

Should possess ability to learn and adapt to new tools and methodologies. Excellent communication skill is a must.