Hiring For Design Verification Eng_ Hyd,Bang,
- Capgemini
- 2 - 7 years
- Hyderabad
- 2 years ago
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Job Description
We are Hiring candidates for Design Verification Engineering to join our team.
Design Verification Engineers
Qualification : BE/B.Tech/Master degree
Exp: 2Years of industry experience to 15 Years
Methodology: UVM
Lang: System Verilog
Verification knowledge is muest
Good knowledge on protocols: Pcle, Ehernet,DDR etc
Should have worked on GLS. Primary Skills Verilog, SV, UVM/OVM, IP Verification, SoC Verification, scripting - Perl, Python, Shell, and Tcl. Secondary Skills Test bench / model / VIP development, Functional coverage, GLS, LEC, Emulation, AMS, ARM, Protocols AHB/AXI/APB, Ethernet, USB, PCIe, I2C, SPI, CAN, Mipi CSI/DSI, LPDDR.
Interested candidates are please share updated resume to ma*************u@ca******i.com
Job Classification
Industry: Electronic Components / SemiconductorsFunctional Area: Engineering - Hardware & Networks,
Role Category: Hardware
Role: Hardware
Employement Type: Full time
Education
Under Graduation: Any GraduatePost Graduation: Post Graduation Not Required
Contact Details:
Company: CapgeminiAddress: ,1,5,6,7 Floors and Basement,Akruti Softech Park,C, NAVI MUMBAI, Maharashtra, India
Location(s): Hyderabad
Keyskills: Design Verification UVM Synthesis ASIC Verification Perl SOC Verification System Verilog
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Capgemini
Capgemini is headquartered in Paris, France and operates in more than 40 countries. They are one of the world’s largest providers of Consulting, Technology, and Outsourcing. Above all, Capgemini is a people company— 120,000 people in North America, Europe, South America and the Asia ...
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